Parallel Port Device Driver Development

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Embedded Systems Software Engineering

Module 10: Parallel Port Device Driver Development

Abstract:

Most personal computers today are equipped with a parallel port, commonly used to connect the computer to a parallel printer. Because it is available on most personal computers, the parallel port is a perfect choice for connection to other peripheral devices. However, communication to peripherals across the parallel port is limited because the interface is traditionally unidirectional and there is no standard specification for the interface. Additionally, although the performance of the PC has dramatically increased, the parallel port has remained the same. This situation has led to the development of a new parallel port standard – IEEE Standard 1284-1994. This standard is based on the original Centronics Standard Parallel Port (SPP) specification, and includes the Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP).

Introduction:

The Standard Parallel Port (SPP) is also known as the Centronics parallel port. Centronics Data Computer Corporation developed the interface in the mid-1960s to be an 8-bit unidirectional parallel host-to-printer connection. The interface became widely used, however, no industry-standard specification was developed to define the interface.

The Centronics "standard" defines a 36-pin champ connector and interface signals for the printer side of the connection. The host side implementation varied widely until the introduction of the IBM PC in 1981. The host parallel port implementation used on the IBM PC, also referred to as the PC parallel interface, became the de facto industry PC parallel port interface. The PC parallel interface defines a 25-pin D Sub connector with 8 unidirectional data lines, four control lines, and five status lines. Because there is no written standard, the timing relationships between the handshaking signals vary widely among printers from different manufacturers, even though they may all claim Centronics compatibility.

The IEEE 1284 standard defines an interface compatible with several distinct operating modes including EPP, ECP, a Compatibility mode for unidirectional communication with existing SPP ports, and Nibble and Byte modes for bidirectional communication with existing unidirectional and bidirectional ports. IEEE 1284 defines three interface connectors: 1284-A, 1284-B and 1284-C. The 1284-A connector is equivalent to the existing 25-pin DSub connector commonly used on the host side of the connection. The 1284-B connector is equivalent to the 36-pin Champ connector commonly used on the peripheral side of the connection. The 1284-C connection is a new 36-pin 0.050 centerline connector. The 1284 specification recommends this connector for both the host and peripheral sides of the connection. Under the IEEE 1284 Daisy Chain Specification, up to eight devices can be connected to a single parallel port. Each daisy chain device has two parallel port connectors – a host and a pass through connector. The host is connected to the host connector on the first device. The pass through connector of the first device is connected to the host connector of the next device, and so on. A device that does not support daisy chaining can be connected to the pass through connector of the last daisy chain device.

The Parallel Port has three commonly used base addresses. The 3BCh base address was originally introduced used for Parallel Ports on early Video Cards. This address then disappeared for a while, when Parallel Ports were later removed from Video Cards. They has now reappeared as an option for Parallel Ports integrated onto motherboards, upon which their configuration can be changed using BIOS. LPT1 is normally assigned base address 378h, while LPT2 is assigned 278h. However this may not always be the case as explained later. 378h & 278h have always been commonly used for Parallel Ports. The lower case “h” denotes that it is in hexadecimal. These addresses may change from machine to machine. When the computer is first turned on, BIOS (Basic Input/Output System) will determine the number of ports you have and assign device labels LPT1, LPT2 & LPT3 to them. BIOS first looks at address 3BCh. If a Parallel Port is found here, it is assigned as LPT1, then it searches at location 378h. If a Parallel card is found there, it is assigned the next free device label. This would be LPT1 if a card wasn't found at 3BCh or LPT2 if a card was found at 3BCh. The last port of call, is 278h and follows the same procedure than the other two ports. Therefore it is possible to have a LPT2 which is at 378h and not at the expected address 278h.

Objective:

Design and Write a parallel port device driver for 25 pin parallel port and implement bacic operations through the driver.

Training Contents for Module 9: Parallel Port Device Driver Development

• Introduction to IEEE 1284 Protocol
• Introduction to Parall Port Architecture
• Device Driver Registration and Initialization
• Accessing The IO Region
• IO Operation through Parallel Port
• Implementing Parallel Port Device Driver in
  • ​Byte Mode
  • Compatibility Mode
  • Nibble Mode
  • ECP Mode
  • EPP Mode

Other Modules in ESSE Training are as follows.

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