Besides general-purpose hardware caches, Intel 80×86 processors include other caches called translation lookaside buffers or TLB to speed up linear address translation. When a linear address is used for the first time, the corresponding physical address is computed through slow accesses to the page tables in RAM. The physical address is then stored in a TLB entry, so that further references to the same linear address can be quickly translated.
The invlpg instruction can be used to invalidate (that is, to free) a single entry of a TLB. In
order to invalidate all TLB entries, the processor can simply write into the cr3 register that
points to the currently used Page Directory.
